Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages

Power dissipation in high performance systems requires more expensive packaging. In this situation, low power VLSI design has assumed great importance as an active and rapidly developing field. As the density and operating speed of CMOS VLSI chip increases, power dissipation becomes more significant due to the leakage current when transistor is OFF. This can be observed in both combinational and sequential circuits. Static power reduction techniques are achieved by means of operating the transistor either in Cut-off or in Saturation region completely and by avoiding the clock in unnecessary circuits. In this work, “Dual sub-threshold voltage supply” technique is used to operate the transistor under either OFF or ON state by applying some voltage at the gate of the MOS transistor. The designed circuits are simulated by using Mentor Graphics Backend Tool. With this technique, nearly 10-75% of the power dissipation is reduced for designed circuits. Thereby, the performance of circuit can be increased. KeywordsDigital circuits, Dual sub-threshold leakage current, Power dissipation, Performance.